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19-3649; Rev 0; 4/05
Overvoltage Protection Controllers with Low Standby Current
General Description
The MAX4843-MAX4846 overvoltage protection controllers protect low-voltage systems against high-voltage faults of up to 28V. When the input voltage exceeds the overvoltage threshold, these devices turn off a low-cost, external n-channel FET(s) to prevent damage to the protected components. An internal charge pump eliminates the need for external capacitors and drives the FET gate for a simple, robust solution. The overvoltage trip level is set to 7.4V (MAX4843), 6.35V (MAX4844), 5.8V (MAX4845), or 4.65V (MAX4846). When the input voltage drops below the undervoltage lockout (UVLO) threshold, the devices enter a low standby current mode (10A). The MAX4843/MAX4844/ MAX4845 have a UVLO threshold of 4.15V, and the MAX4846 has a UVLO threshold of 2.5V. In addition to the single FET configuration, the devices can be configured with back-to-back external FETs to prevent currents from being back-driven into the adapter. An additional feature includes a 15kV ESD-protected input when bypassed with a 1F capacitor to ground. All devices are offered in a small (1.5mm x 1.0mm) 6-pin DFN package and are specified for operation over the -40C to +85C temperature range.
Features
o Overvoltage Protection Up to 28V o Preset 7.4V, 6.35V, 5.8V, or 4.65V Overvoltage Trip Level o Low (10A) Undervoltage Lockout Standby Current o Drives Low-Cost n MOSFET o o o o Internal 50ms Startup Delay Internal Charge Pump Overvoltage Fault FLAG Indicator 6-Pin (1.5mm x 1.0mm) DFN Package
MAX4843-MAX4846
Ordering Information
PART* MAX4843ELT MAX4844ELT MAX4845ELT MAX4846ELT PINPACKAGE 6 DFN 6 DFN 6 DFN 6 DFN UVLO (V) 4.15 4.15 4.15 2.50 OVLO (V) 7.40 6.35 5.80 4.65 TOP MARK BE BF BG BH
*All devices are specified over the -40C to +85C temperature range.
Applications
Cell Phones Digital Still Cameras PDAs and Palmtop Devices MP3 Players
Typical Operating Circuit
Pin Configuration
INPUT +1.2V TO +28V
TOP VIEW
N OUTPUT IN 1 1 IN GATE 4 GND 2 VIO 6 N.C.
1F
MAX4843- MAX4846
5
N.C.
MAX4843- MAX4846
2 GND FLAG 3
FLAG 3
4
GATE
DFN
________________________________________________________________ Maxim Integrated Products
1
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Overvoltage Protection Controllers with Low Standby Current MAX4843-MAX4846
ABSOLUTE MAXIMUM RATINGS
IN to GND ..............................................................-0.3V to +30V GATE to GND ........................................................-0.3V to +12V FLAG to GND ..........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 6-Pin DFN (derate 2.1mW/C above +70C) .........167.7mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .................................................... +150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis SYMBOL VIN UVLO VIN falling MAX4843/MAX4844/MAX4845 MAX4846 CONDITIONS MIN 1.2 3.9 2.3 4.15 2.5 41 25 MAX4843 Overvoltage Trip Level OVLO VIN rising MAX4844 MAX4845 MAX4846 MAX4843 Overvoltage Lockout Hysteresis MAX4844 MAX4845 MAX4846 IN Supply Current UVLO Supply Current Gate Voltage GATE Pulldown Current FLAG Output Low Voltage FLAG Leakage Current IIN IUVLO VGATE IPD VOL MAX4843/MAX4844/MAX4845 MAX4846 VIN = 3.8V VIN = 2.2V 1A load MAX4843/MAX4844/MAX4845 MAX4846 MAX4843/MAX4844/MAX4845 MAX4846 9 7.5 10 7.0 6.0 5.5 4.35 7.4 6.35 5.8 4.65 75 65 55 50 70 60 10 8 9.83 7.85 27 0.4 1 120 110 22 18 10 8.0 A A V mA V A mV 7.8 6.7 6.1 4.95 V TYP MAX 28.0 4.4 2.7 UNITS V V mV
MAX4843/MAX4844/MAX4845 MAX4846
VIN > OVLO, VGATE = 5.5V ISINK = 1mA, FLAG deasserted VFLAG = 5.5V, FLAG asserted
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Overvoltage Protection Controllers with Low Standby Current
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER TIMING Startup Delay tSTART tBLANK VIN = UVLO rising to VGATE = 0.3V rising (Figure 1) VGATE = 0.3V rising to VFLAG = 0.3V falling (Figure 1) VGATE = 0.3V to 8V (MAX4843/MAX4844/MAX4845), VGATE = 0.3V to 7V (MAX4846) (Figure 1) VIN rising at 1V/s from 5V to 8V (MAX4843/MAX4844/MAX4845) or from 4V to 7V (MAX4846) to VGATE = 0.3V (Figure 2) VIN rising at 1V/s from 5V to 8V (MAX4843/MAX4844/MAX4845) or from 4V to 7V (MAX4846), to VFLAG = 2.4V, RFLAG = 10k to 3V (Figure 2) VIN rising at 1V/s from 0V to 9V, time from VIN = 5V to IGATE = 80% of IPD (Figure 3) 20 50 80 ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX4843-MAX4846
FLAG Blanking Time
20
50
80
ms
Gate Turn-On Time
tGON
10
ms
Gate Turn-Off Time
tGOFF
6
20
s
FLAG Assertion Delay
tFLAG
5.8
s
Initial Overvoltage Fault Delay
tOVP
1.5
s
Note 1: All devices are 100% tested at +25C. Electrical limits across the full temperature range are guaranteed by design and correlation.
Typical Operating Characteristics
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX4843)
MAX4843-46 toc01
REVERSE CURRENT vs. OUTPUT VOLTAGE (MAX4843)
100 REVERSE CURRENT (A) 10 1 0.1 0.01 0.001 BACK-TO-BACK FET SINGLE FET
MAX4843-46 toc02
GATE VOLTAGE vs. INPUT VOLTAGE (MAX4843/MAX4844/MAX4845)
MAX4843-46 toc03
100
1000
15 MAX4844 MAX4843
80 SUPPLY CURRENT (A)
12 GATE VOLTAGE (V)
MAX4845 9
60
40
6
20
0.0001 0.00001
3
0 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V)
0.000001 1 2 4 3 5 6 OUTPUT VOLTAGE (V) 7
0 3 4 5 6 7 8 INPUT VOLTAGE (V)
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Overvoltage Protection Controllers with Low Standby Current MAX4843-MAX4846
Typical Operating Characteristics (continued)
(VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA = +25C, unless otherwise noted.)
GATE VOLTAGE vs. INPUT VOLTAGE (MAX4846)
MAX4843-46 toc04
GATE VOLTAGE vs. INPUT VOLTAGE (MAX4843)
MAX4843-46 toc05
POWER-UP RESPONSE
MAX4843-46 toc06
10
10.50
8 GATE VOLTAGE (V)
10.25 GATE VOLTAGE (V)
GATE CURRENT = 0
VIN 0 VGATE
5V/DIV
6
10.00 0 9.75 GATE CURRENT = 1A VFLAG 0
5V/DIV
4
2
5V/DIV
0 1 2 3 4 5 6 INPUT VOLTAGE (V)
9.50 3 4 5 6 7 8 20ms/DIV INPUT VOLTAGE (V)
POWER-UP RESPONSE
MAX4843-46 toc07
OVERVOLTAGE RESPONSE
MAX4843-46 toc08
POWER-UP OVERVOLTAGE RESPONSE
MAX4843-46 toc09
8V VIN 0 VOUT 0 IIN 0 VFLAG 0 20ms/DIV 4s/DIV 5V/DIV VFLAG 0 20s/DIV 1A/DIV IGATE 0 5V/DIV 5V/DIV VGATE 0 5V/DIV VIN 0 10V/DIV VGATE 10mA/DIV VFLAG 0 0 5V/DIV 5V/DIV VIN 0 2V/DIV 8V 5V/DIV
Pin Description
PIN 1 2 3 4 5, 6 NAME IN GND FLAG GATE N.C. FUNCTION Voltage Input. IN is both the power-supply input and the overvoltage sense input. Bypass IN to GND with a 1F capacitor or larger. Ground Fault Indication Output. FLAG is asserted high during undervoltage lockout and overvoltage lockout conditions. FLAG is deasserted during normal operation. FLAG is an open-drain output. Gate-Drive Output. GATE is the output of an on-chip charge pump. When VUVLO < VIN < VOVLO, GATE is driven high to turn on the external n-channel MOSFET(s). No Connection. Not internally connected.
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Overvoltage Protection Controllers with Low Standby Current
Functional Diagram
MAX4843-MAX4846
IN
5.5V REGULATOR
2x CHARGE PUMP
GATE DRIVER
GATE
GND UVLO AND OVLO DETECTOR
CONTROL LOGIC AND TIMER
MAX4843- MAX4846
FLAG
5V VIN VUVLO tGON 8V tSTART VGATE 0.3V VGATE 0.3V VIN 5V tGOFF VOVLO tFLAG
VFLAG tBLANK
0.3V
VFLAG
2.4V
Figure 1. Startup Timing Diagram
Figure 2. Shutdown Timing Diagram
VIN 0V
VOVLO
tOVP 80% IGATE
Figure 3. Power-Up Overvoltage Timing Diagram
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Overvoltage Protection Controllers with Low Standby Current MAX4843-MAX4846
Detailed Description
The MAX4843-MAX4846 provide up to 28V overvoltage protection for low-voltage systems. When the input voltage exceeds the overvoltage trip level, the MAX4843-MAX4846 turn off a low-cost external n-channel FET(s) to prevent damage to the protected components. An internal charge pump (see the Functional Diagram) drives the FET gate for a simple, robust solution. On power-up, the device waits for 50ms before driving GATE high. The open-drain FLAG output is kept at high impedance for an additional 50ms after GATE goes high before deasserting. The FLAG output asserts high immediately to an overvoltage fault.
Device Operation
The MAX4843-MAX4846 have an on-board state machine to control device operation. A flowchart is shown in Figure 4. On initial power-up, if VIN < UVLO or if VIN > OVLO, GATE is held at 0V, and FLAG is high. If UVLO < VIN < OVLO, the device enters startup after a 50ms internal delay. The internal charge pump is enabled, and GATE begins to be driven above VIN by the internal charge pump. FLAG is held high during startup until the FLAG blanking period expires, typically 50ms after the GATE starts going high. At this point the device is in its on state. At any time if VIN drops below UVLO or VIN is greater than OVLO, FLAG is driven high and GATE is driven to ground.
Undervoltage Lockout (UVLO)
The MAX4843/MAX4844/MAX4845 have a fixed 4.15V typical UVLO level, while the MAX4846 has a 2.5V typical UVLO. When VIN is less than the UVLO, the GATE driver is held low and FLAG is asserted.
Overvoltage Lockout (OVLO)
The MAX4843 has a 7.4V typical OVLO; the MAX4844 has a 6.35V typical OVLO; and the MAX4845 has a 5.8V typical OVLO. The MAX4846 has a 4.65V typical overvoltage threshold. When VIN is greater than OVLO, the GATE driver is held low and FLAG is asserted.
STANDBY GATE = 0 FLAG = HIGH VIN > UVLO
VIN < UVLO
TIME STARTS COUNTING t = 50ms
FLAG Output
The open-drain FLAG output is used to signal to the host system that there is a fault with the input voltage. FLAG asserts immediately to an overvoltage fault. FLAG is held high for 50ms after GATE turns on before deasserting. Connect a pullup resistor from FLAG to the logic I/O voltage of the host system.
OVLO CHECK GATE = 0 FLAG = HIGH VIN < OVLO VIN > OVLO STARTUP GATE DRIVEN HIGH FLAG = HIGH t = 50ms
GATE Driver
An on-chip charge pump is used to drive GATE above IN, allowing the use of low-cost n-channel MOSFETs. The charge pump operates from the internal 5.5V regulator. The actual GATE output voltage tracks approximately two times VIN until VIN exceeds 5.5V or the OVLO trip level is exceeded, whichever comes first. The MAX4843 has a 7.4V typical OVLO, therefore GATE remains relatively constant at about 10.5V for 5.5V < VIN < 7.4V. The MAX4845 has a 5.8V typical OVLO, but this can be as low as 5.5V. The GATE output voltage as a function of input voltage is shown in the Typical Operating Characteristics.
ON GATE HIGH FLAG = LOW
Figure 4. State Diagram
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Overvoltage Protection Controllers with Low Standby Current
Applications Information
MOSFET Configuration
The MAX4843-MAX4846 can be used with either a single MOSFET configuration as shown in the Typical Operating Circuit, or can be configured with a back-toback MOSFET as shown in Figure 5. The back-to-back configuration has almost zero reverse current when the input supply is below the output. If reverse current leakage is not a concern, a single MOSFET can be used. This approach has half the loss of the back-to-back configuration when used with similar MOSFET types and is a lower cost solution. Note that if the input is actually pulled low, the output is also pulled low due to the parasitic body diode in the MOSFET. If this is a concern, the back-to-back configuration should be used. In a typical application of the MAX4846, an external adapter with built-in battery charger is connected to IN and a battery is connected to the source of the external FET. When the adapter is unplugged, IN is directly connected to the battery through the external FET. Since the battery voltage is typically greater than 3V, the GATE voltage stays high and the device remains powered by the battery.
INPUT +1.2V TO +28V N N
MAX4843-MAX4846
1 1F
IN
GATE
4 VIO
MAX4843- MAX4846
2 GND FLAG 3
Figure 5. Back-to-Back External MOSFET Configuration
IN Bypass Considerations
For most applications, bypass IN to GND with a 1F ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 30V absolute maximum rating on IN. The MAX4843-MAX4846 provide protection against voltage faults up to 28V, but this does not include negative voltages. If negative voltages are a concern, connect a Schottky diode from IN to GND to clamp negative input voltages.
MOSFET Selection
The MAX4843-MAX4846 are designed for use with either a single n-channel MOSFET or dual back-to-back n-channel MOSFETs. In most situations, MOSFETs with RDS(ON) specified for a VGS of 4.5V work well. If the input supply is near the UVLO maximum of 3.5V, consider using a MOSFET specified for a lower VGS voltage. Also the VDS should be 30V for the MOSFET to withstand the full 28V IN range of the MAX4843-MAX4846. Table 1 shows a selection of MOSFETs appropriate for use with the MAX4843-MAX4846.
ESD Test Conditions
ESD performance depends on a number of conditions. The MAX4843-MAX4846 are protected from 15kV typical ESD on IN when IN is bypassed to ground with a 1F ceramic capacitor.
Table 1. MOSFET Suggestions
PART Si5902DC Si1426DH FDC6561AN FDC6305N FDG315N CONFIGURATION/ PACKAGE Dual/1206-8 Single/SSOT-6 Dual/SSOT-6 Dual/SSOT-6 Single/SC70-6 VDS MAX (V) 30 30 30 20 30 RON at 4.5V (m) 143 115 145 80 160 Fairchild Semiconductor www.fairchildsemi.com MANUFACTURER Vishay Siliconix www.vishay.com
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Overvoltage Protection Controllers with Low Standby Current MAX4843-MAX4846
Human Body Model
Figure 6 shows the Human Body Model and Figure 7 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5k resistor. help users design equipment that meets Level 3 of IEC 1000-4-2, without additional ESD-protection components. The main difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2. Because series resistance is lower in the IEC 1000-4-2 ESD test model (Figure 8), the ESD withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 9 shows the current waveform for the 8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized.
IEC 1000-4-2
Since January 1996, all equipment manufactured and/or sold in the European Union has been required to meet the stringent IEC 1000-4-2 specification. The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX4843-MAX4846
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5 DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
RC 50 to 100 CHARGE-CURRENTLIMIT RESISTOR
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 100pF
STORAGE CAPACITOR
Cs 150pF
STORAGE CAPACITOR
Figure 6. Human Body ESD Test Model
Figure 8. IEC 1000-4-2 ESD Test Model
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK
I 100% 90%
10% tr = 0.7ns to 1ns 30ns 60ns t
tDL CURRENT WAVEFORM
Figure 7. Human Body Model Current Waveform
Figure 9. IEC 1000-4-2 ESD Generator Current Waveform
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Overvoltage Protection Controllers with Low Standby Current
Chip Information
PROCESS TECHNOLOGY: BiCMOS
MAX4843-MAX4846
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
3
A
4 TOPMARK 2
e
5
b
6 PIN 1 0.075x45
PIN 1 INDEX AREA
AAA
1
L E
L2
3
2 A A
1
D TOP VIEW
A1 SIDE VIEW
L1 BOTTOM VIEW
b
A A1 D E L L1 L2 b e
COMMON DIMENSIONS MIN. 0.64 -1.45 0.95 0.30 --0.17 NOM. 0.72 0.20 1.50 1.00 0.35 --0.20 0.50 BSC. MAX. 0.80 -1.55 1.05 0.40 0.08 0.05 0.23
SECTION A-A
TITLE:
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
APPROVAL DOCUMENT CONTROL NO. REV.
-DRAWING NOT TO SCALE-
21-0147
C
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
6L UDFN.EPS

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